1. Field of the Invention
This invention relates generally to the emulation of computing systems, and more particularly to a high performance emulation system and method for emulating a computing system through software pipelining and synchronization.
2. Description of the Prior Art
Modern computers are able to achieve much of their high performance due to the parallel operation of the internal hardware. For example, a pipelined computer may be in the process of executing more than one instruction in each hardware cycle. With a deep pipeline, a register file update for one instruction can be performed at the same time as the arithmetic operation for the following instruction, the operand fetch for the third instruction, the address generation for a fourth instruction, the instruction decode for a fifth, and so on. Within each pipeline stage additional parallel operations can take place.
A prior art software emulation technique involves emulating instructions on a host emulation computer by executing a series of native mode instructions which emulate the instructions of the target system. The target system is the system to be emulated, and native mode instructions are instructions which can be executed by the processing environment of the host emulation computer. In such an emulation system, one native mode instruction simulates the operation of a small portion of one stage of a corresponding target system hardware operation. The result is that it may require hundreds of serially executed native mode instructions to emulate a single target system instruction which normally triggers various simultaneous hardware activities.
There is a need, therefore, for a high speed, parallel software emulation system which reduces emulation time. The present invention allows for the use of multiple activities and processors, if desired, to perform emulation in a pipelined fashion. The invention also provides an efficient synchronization mechanism for passing information from one software emulation stage to another software emulation stage. The present invention therefore provides a solution to the aforementioned emulation speed problem and other problems, and offers other advantages over the prior art.
It is a primary object of this invention to provide an improved hardware emulation system.
It is another object of the invention to enhance the speed in which an emulation system can emulate a target system.
It is yet another object of the invention to provide an improved emulation system wherein software emulates hardware functions of the target system.
It is still another object to provide software emulation routines which are executed in parallel.
Still another object of the invention is to provide software emulation routines wherein software activities are executed in a parallel, pipelined fashion,
It is yet another object of the invention to forward information from one software activity to the next software activity in the software emulation pipeline, and to forward the information when a particular stage has completed its activity and when the next stage is ready to accept more information.
Other more detailed objectives will become apparent from a consideration of the Drawings and the Detailed Description of the Preferred Embodiment.